April 3, 2007

 

University of Texas – Austin

Thompson Conference Center

 

7:45 – 8:15      Breakfast and Registration in Lobby

 

8:15 – 8:30      Welcome and Introductions from General Co-chair and Committee,

                          Wendy Bartlett (HP), Pia Sanda (IBM)

Welcome from local sponsor and Steering Committee – Chuck Moore (AMD)

 

8:30 – 10:30    Soft error characterization

Chair: Zbigniew Kalbarczyk (University of Illinois at Urbana-Champaign)

·        IBM POWER6 Processor Soft Error Tolerance Analysis Using Proton Irradiation, Jeffrey Kellington, Ryan McBeth, Pia Sanda and Ronald Kalla (IBM) Paper Presentation

 

·        Assessing the impact of scaling on the efficacy of spatial redundancy based mitigation schemes for terrestrial applications, Norbert Seifert, Victor Zia and Balkaran Gill, (Intel) Paper Presentation

 

·        Fast and Physically-Accurate Estimation of Single Event Transient Pulses From Radiation-Induced Transient Currents Measured in a Single MOSFET: A Simulation-Based Case Study in Bulk CMOS Logic Circuits, Daisuke Kobayashi, Kazuyuki Hirose, Hirokazu Ikeda and Hirobumi Saito, ISAS/JAXA Paper

 

·        Accelerated Testing of a 90nm SPARC64 V Microprocessor for Neutron SER, Hisa Ando, Ken Seki, Satoru Sakashita, Masatoshi Aihara, Ryuji Kan, Kenji Imada, Masaru Itoh, Masamichi Nagai, Yoshiharu Tosaka, (Fujitsu), Keiji Takahisa and Kichiji Hatanaka (Osaka University) Paper (Presentation not available)

 

10:30 – 11:00  Break

 

11:00 – 12:00  Wearout

Chair: Kanak Agarwal (IBM)

·        Circuit Failure Prediction, Mridul Agarwal, Subhasish Mitra (Stanford), Bipul Paul (Toshiba), Ming Zhang (Intel) Paper

 

·        Detecting Emerging Wearout Faults, Jared Smolens, Brian Gold, James Hoe, Babak Falsafi and Ken Mai (Carnegie Mellon University) Paper Presentation

12:00 – 12:45  Lunch in Room 3.102

 

12:45 – 2:00    Dessert and Poster Presentations in Room 3.102

Chair: William Robinson (Vanderbilt University),

Sarita Adve (University of Illinois at Urbana – Champaign)

·        Fingerprinting Across On-Chip Memory Interconnects, Srinivas Chellappa, Frederic de Mesmay, Jared Smolens, Babak Falsafi, James Hoe and Ken Mai (Carnegie Mellon University)

 

·        New simulation methods for accurate SET characterization; layout effects and multiple-node transients, Klas Lilja (Robust Chip)

 

·        Fixed Priority Allocation and Scheduling Scheme for Energy Efficient Fault Tolerance in Real-Time Multiprocessor Systems, Tongquan Wei, Piyush Mishra, (Michigan Technological University), Han Liang and Kaijie Wu (University of Illinois at Chicago)

 

·        Soft Error Vulnerability of Iterative Linear Algebra Methods, Grigory Bronevetsky and Bronis R. de Supinski (Lawrence Livermore National Laboratory)

 

·        Soft Error Derating of IBM POWER6 Microprocessor Using Statistical Fault Injection, John Schumann, Prabhakar Kudva, Jeffrey Kellington, and Pia Sanda (IBM)

 

·        Ion Microprobe Measurement of Sensitive Volumes in a 0.25μm CMOS Flip-flop, Jeff Wilkinson, Mark Porter, Scott Morrison (Medtronic), Robert Reed, Brian Sierawski, Kevin Warren, Robert Weller, Marcus Mendenhall (Vanderbilt University)

 

2:00 – 3:30      Error Detection in Processors

Chair: Dean Liberty (AMD)

·                       Achieving fault detection & performance on CMPs, Gordon Bell and Mikko Lipasti (University of Wisconsin) Paper Presentation

 

·                       Exploiting Slack for Low Overhead Soft Error Reliability, Premkishore Shivakumar and Stephen Keckler (University of Texas at Austin) Paper

 

·                       Critical Variable Recomputation for Transient Error Detection, Karthik Pattabiraman, Zbigniew Kalbarczyk and Ravishankar Iyer (University of Illinois at Urbana-Champaign) Paper Presentation

 

3:30 – 4:00      Break

 

4:00 – 5:30      Panel 1 – Soft Error Derating

                        Moderator: Jacob Abraham (University of Texas – Austin)

                                    Panelists

                                                                Hisashige Ando, Fujitsu

Sarita Adve, University of Illinois

                                                Ron Kalla, IBM

Shubu Mukherjee, Intel

 

6:00                 Reception and Dinner at the University of Texas Club

                        Speaker: Brad McCredie (IBM)

 

 

 

 

 

 


 

 

                                            

 

April 4, 2007

 

 

7:45 – 8:30      Breakfast in Lobby

 

8:30 – 10:30    System-level Architecture

Chair: Michael Orshansky (University of Texas - Austin)

·                       Towards a Software-Hardware Co-Designed Resilient System, Man-Lap Li, Pradeep Ramachandran, Sarita Adve, Vikram Adve and Yuanyuan Zhou (University of Illinois at Urbana-Champaign) Paper

 

·                       Error-Resilient System Architecture (ERSA) For Probabilistic Applications, Jason Bau, Subhasish Mitra (Stanford), Quinn Jacobson, Richard Hankins (Nokia), Bratin Saha and Ali-Reza Adl-Tabatabai (Intel) Paper

 

·                       Impact of Soft Errors in a Brake-by-Wire System, Daniel Skarin, Johan Karlsson (Chalmers University of Technology), Martin Sanfridson (Volvo) Paper Presentation

 

·                       Motivating Commodity Multi-Core Processor Design for System-level Error Protection, Nidhi Aggarwal, Kewal K. Saluja, James E. Smith (University of Wisconsin), Parthasarthy Ranganathan, Norman P. Jouppi and George Krejci (HP) Paper Presentation

 

10:30 – 11:00  Break

 

11:00 – 12:30  Panel 2 – Silicon Errors in Modern Electronics: What are the Main Threats?

Moderator: Dennis Abts (Cray)

                                                Panelists

                                                Sarah Michalak – LANL

Shi-Jie Wen – CISCO

Josep Torrellas – University of Illinois

Cristian Constantinescu – AMD 

Alan Wood – Sun Microsystems

 

12:30 – 1:30    Lunch in Room 3.102
1:30 – 3:30      Memory Soft Errors

Chair: Steve Keckler (University of Texas – Austin)

  • Neutron-Induced Logic Soft Errors in DRAM Technology and Their Impact on Reliable Server Memory, Guenter Schindlbeck (Infineon) and Charles Slayman (SUN) Paper (corrected) Presentation

 

  • Architectural Support for Mitigating DRAM Soft Errors in Large-Scale Supercomputers, Dennis Abts, John Thompson and Gerald Schwoerer (Cray) Paper

 

  • A Low Cost Code-Based Methodology for Tolerating Multiple Bit Upsets in Memories, Avijit Dutta and Nur Touba (University of Texas at Austin) Paper Presentation

 

  • Reducing Soft Error Vulnerability of Data Caches, Xavier Vera, Jaume Abella, Antonio Gonzalez and Ronny Ronen (Intel) Paper

 

3:30 – 4:00      Break

 

4:00 – 5:30      Soft Error Protection

Chair: Ming Zhang (Intel)

·                       Soft Error Protection via Fault-Resilient Data Representations, Mohammed Latif, Ravi Ramaseshan, and Frank Mueller (NC State University) Paper

 

·                       Efficient Flip-Flop Designs for SET/SEU Mitigation with Tolerance to Crosstalk Induced Signal Delays, Aditya Jagirdar, Roystein Oliveira (Rutgers University) and Tapan Chakraborty (Lucent) Paper Presentation

 

·                       Reliability in the Shadow of Long-Stall Instructions, Vilas Sridharan, David Kaeli (Northeastern University), and Arijit Biswas (Intel) Paper Presentation

 

5:30                 Closing Remarks

 

With grateful support from our sponsors!

 

   

 

           

 

   

 

Thanks for support from the NASA Electronic Parts and Packaging Program!